In the continuing development of faster and more powerful computer systems, reduced instruction set computer (RISC) processors have become commonplace. Increased advances in the field of RISC processors have led to the development of superscalar processors. Superscalar processors, as their name implies, perform functions not commonly found in traditional scalar microprocessors. Included in these functions are multiple execution units with out-of-order and speculative instruction execution.
In most superscalar processors, some classes of instructions may take a variable time to execute. In other words, when one of these instructions is to be executed, there may be no indication of the number of cycles required to complete execution. For example, executing a storage reference instruction includes three major steps: address generation, address translation, and cache access. These steps are executed through a pipeline. Although high end processors may achieve some overlap of these steps, there may still be difficulty in completing one or more of these operations. This is particularly true of address translations and cache accesses. Such difficulties will delay execution of the storage reference instruction, possibly causing the instruction to be executed over a larger number of cycles. However, it is desirable to optimize the hardware for the more frequent short execution cases, rather than burden all cases with the delay associated with the slowest cases.
A number of conventional systems fall into two categories. Some conventional systems are unable to account for differences in the time required to execute the steps of an instruction. These systems must be designed such that the longest instruction, no matter how infrequent, can always be executed. Other conventional systems can account for some expansion of the time required to execute an instruction. However, this function is split among multiple components which use the results of the portion of the instruction that has already been executed.
Accordingly, what is needed is a system and method for providing dynamic expansion of an instruction execution pipeline which does not split the function among components depending on the reason for the delay. The present invention addresses such a need.